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technical brief o k i a s i c p r o d u c t s january 1997 W712 universal serial bus controller 0.5 m m technology mega macrofunction
n n oki semiconductor contents description................................................................................................................................................................ 1 features ..................................................................................................................................................................... 1 signal descriptions .................................................................................................................................................. 4 functional description ............................................................................................................................................ 7 protocol engine .................................................................................................................................................. 7 dpll..................................................................................................................................................................... 7 timer .................................................................................................................................................................... 7 status/control ................................................................................................................................................... 7 fifo control ...................................................................................................................................................... 7 application interface ......................................................................................................................................... 8 frame timer synthesizer................................................................................................................................... 8 remote wakeup.................................................................................................................................................. 8 usb transfers ..................................................................................................................................................... 8 usb interface ...................................................................................................................................................... 8 glossary ..................................................................................................................................................................... 9 appendix ................................................................................................................................................................. 10
1 oki semiconductor W712 usb device controller 0.5 m m technology mega macrofunction description the universal serial bus (usb) device controller mega macrofunction is a featured element in oki? 0.5 m m sea of gates (sog) and customer structured array (csa) families. oki's usb mega macrofunction provides a usb interface, control/status block, fifo control, and application interface in two highly inte- grated submodules for system design interfaces based on the usb protocol. the submodule partitioning allows custom configurations to be easily developed. the usb mega macrofunction connects an industry standard usb interface with a microprocessor-style parallel application interface. this straightforward interface permits easy integration of the usb mega macrofunction to the target application. using oki? usb mega macrofunction, designers can reduce development time, risk, and introduce their usb based products to market faster. oki? W712 usb device controller mega macrofunction provides a complete usb device interface solution and is fully compliant with the universal serial bus 1.0 specification. for more details on the universal serial bus 1.0 specification, refer to www.usb.org. features supported asic families family name family type msm13r0000 sea of gates msm98r000 customer structured array usb 1.0 compliant full-speed (12 mb/sec) and low-speed (1.5 mb/sec) support microprocessor-style parallel application interface supports isochronous, control, interrupt and bulk transfers supports four transmit fifo? - three 64 byte - one 2 kbyte (2-level) supports four receive fifo? - three 64 byte - one 2 kbyte (2-level) supports one control endpoint and six additional endpoint addresses expandable up to 32 endpoint addresses customizable to specific application requirements
n W712 usb device controller n 2 oki semiconductor figure 1. logic symbol recommended operating conditions (v ss = 0 v) parameter symbol min. typ. max unit power supply voltage v dd 2.7 3.3 3.6 v operating temperature t j -40 +25 +85 c mega macrofunction characteristics mega macrofunction description logic gate count logic pin count W712 usb device controller 15797 139 usb_dpin usb_dmin usb_rxd usb_dpout usb_dmout usb_txenb full_spden sel_ext_pll sys_clock [7:0]ma [7:0]md mrdyb [7:0]pd [3:0]pkt_rdy setup_rdy [7:0]trx_out_data [7:0]rcv_out_data [7:0]trx_in_data [2:0]trx_sel [8:0]trx_wr_ptr [6:0]trx_wrb [7:0]rcv_in_data [2:0]rcv_sel [6:0]rcv_wrb fifo interface usb interface application interface W712 sys_reset testmode mwr_rdb setup_rdy2 iso_err usb_reset validsof validin validout [8:0]trx_rd_ptr [8:0]rcv_wr_ptr [8:0]rcv_rd_ptr osc_clk usb_clk_ext usb_rxd_out dpll interface
n W712 usb device controller n 3 oki semiconductor figure 2. W712 block diagram figure 3. example usb mega macrofunction application protocol engine fifo control status/control application interface to application module to fifo? (control) to usb transceiver to fifo? (data path) to fifo? (data path) clock dpll W712b z712a W712 optional external dpll W712 mega macrofunction application interface external module i/o usb transceiver protocol engine fifo control status/ control fifo(s)/ data mux(s) application module clock usb cable asic data path data path dpll
n W712 usb device controller n 4 oki semiconductor signal descriptions usb interface signal type assertion description usb_dpin input usb data plus in. this input and the usb_dmin input are the received single ended data from the usb transceiver. the table below shows values and results for these signals. usb_dmin input usb data minus in. this input and the usb_dpin input are the received single ended data from the usb transceiver. see the table for the usb_dpin description, above, for values and results of these signals. usb_dpout output usb data plus out . this output and the usb_dmout signal come from the usb transmit engine and drive the differential output buffers. the table below shows values and results for these signals. usb_dmout output usb data minus out. this output and the usb_dpout signal come from the usb transmit engine and drive the differential output buffers. see the signal description for usb_dpout, above, for a description of signal values and results. usb_rxd input usb differential received data. this input comes from the usb differential receiver, and connects to the W712 mega macrofunction. usb_txenb output low usb 3-state output enable. this signal connects to the transceiver eb input through an inverter gate. when the W712 mega macrofunction asserts this signal low, the transceiv- er transmits data on the usb bus. see appendix for the usb transceiver data sheets. usb_dpin usb_dmin result 0 0 se0 0 1 logic ? 1 0 logic ? 1 1 undefined usb_dpout usb_dmout result 0 0 se0 0 1 logic ? 1 0 logic ? 1 1 undefined
n W712 usb device controller n 5 oki semiconductor application interface signal type assertion description sys_clock input clock . attach a 12-mhz clock signal to this input for full-speed operation and 1.5 mhz for low-speed operation. sys_reset input high W712 reset. asserting this signal high resets the W712 mega macrofunction. the appli- cation module is required to assert this signal at power-on. mwr_rdb input write/read select. when external application logic asserts this signal high, the applica- tion is in write mode. when asserted low, the application is in read mode. external application logic asserts this signal high when writing data to the transmit fifos or to the register files. external application logic asserts this signal low when reading data from the receiving fifos or from the register files. the register files contain information describ- ing the function and transaction status. usb_reset output high usb reset . this is the reset signal from the usb device controller. [7:0]ma input address bus. these eight inputs receive the address of the register files in the usb device controller. [7:0]md input input data bus. these eight inputs receive the data to be stored in the register files or transmit fifos. mrdyb input low data strobe. when asserted low and in write mode, the data on the [7:0]md signal lines are valid for writing. when asserted low and in read mode, the data on the [7:0]pd signals are valid for reading. [7:0]pd output output data bus . these eight outputs transmit data received from either the register files or the receive fifos. [3:0]pkt_rdy output high packet ready . when the W712 asserts this signal, it indicates that one of the four receive fifos contains valid data. the application reads the data through the [7:0]pd bus. full_spden input usb full speed enable. the application module sets this pin to ??to select full-speed operation and ??to select low-speed operation. setup_rdy output high setup ready. asserting this signal high indicates an 8-byte setup data has been re- ceived from the usb bus. iso_err output high isochronous error. used for loopback testing or to indicate isochronous data has been re- ceived with data1 pid. validsof output high valid sof . this signal is asserted for two bit times, asynchronous to sys_clock, and indi- cates a valid sof token is received when asserted high. sel_ext_pll input high select external pll . asserting this signal high selects the external pll option. setup_rdy2 output high second setup ready . asserting this signal high indicates a new 8-byte setup data has been received, while internally the device controller still sees the ?etup_rdy?signal assert- ed. this signal will be asserted for two bit times, asynchronous to sys_clock. testmode input high testmode . asserting this signal invokes a loopback test mode. validin output high valid in . asserted for two bit times, asynchronous to sys_clock, and indicates a valid in token is received when asserted high. validout output high valid out . asserted for two bit times, asynchronous to sys_clock, and indicates a valid out token is received when asserted high.
n W712 usb device controller n 6 oki semiconductor fifo interface signal type assertion description [7:0]trx_out_data input transmit fifo(s} data output . output data from the transmission ram selected for read- ing. [7:0]rcv_out_data input receive fifo(s) data output . output data from the receiving ram selected for reading. [7:0]trx_in_data output transmit fifo(s) data input . input data to all transmission rams. [2:0]trx_sel output high transmit fifo(s) select . selects one of the seven transmission rams for reading. [8:0]trx_wr_ptr output transmit fifo(s) write pointer . write address to all transmission rams. [8:0]trx_rd_ptr output transmit fifo(s) read pointer . read address to all transmission rams. [6:0]trx_wrb output low transmit fifo(s) write strobe . write enable. one bit per transmission ram. [7:0]rcv_in_data output receive fifo(s) data input . input data to all receiving rams. [2:0]rcv_sel output high receive fifo(s) select . selects one of the seven receiving rams for reading. [8:0]rcv_wr_ptr output receive fifo(s) write pointer . write address to all receiving rams. [8:0]rcv_rd_ptr output receive fifo(s) read pointer . read address to all receiving rams. [6:0]rcv_wrb output low receive fifo(s) write strobe . write enable. one bit per receiving ram. dpll interface signal type assertion description osc_clk input oscillator clock . attach a 48 mhz clock signal for full-speed operation or a 6 mhz clock signal for low-speed operation. usb_clk_ext input usb clock external . this is the output clock signal from an external dpll. this clock should run at 12 mhz for full-speed operation or 1.5 mhz for low-speed operation. if an external dpll is not used, this pin should be connected to vdd or gnd. usb_rxd_out output synchronized usb differential received data . this signal comes from the usb differen- tial receiver and is synchronized with the oscillator input. this signal connects to the ex- ternal dpll if it is used.
n W712 usb device controller n 7 oki semiconductor functional description the W712 controller consists of two submodules, the z712a hard macro, and the W712b soft macro, each containing multiple function blocks. the z712a includes the protocol engine, dpll, and timer blocks. the W712b includes the status/control, fifo control, application interface, frame timer synthesizer, and remote wakeup blocks. protocol engine the protocol engine handles the usb communication protocol. it performs packet sequencing, signal generation/detection, crc generation/checking, nrzi data encoding, bit-stuffing and packet id (pid) generation/decoding. dpll the digital phase locked loop extracts the clock and data from the usb differential received data. timer the timer block monitors idle time on the usb bus. status/control the status/control block uses transfer type and fifo state information to manage the reception and transmission of usb data. it monitors the transaction status and communicates control events to the appli- cation via the application interface. fifo control the fifo control block manages all fifo operations for transmitting and receiving usb data sets. the W712 supports eight fifos (four transmit and four receive). they can be configured as described in the table below. endpoints 3 and 7 are 2-level fifos which support up to two separate data sets of variable sizes. all fifos have flags that detect a full or empty fifo and have the capability of re-transmitting or re-receiving the current data set. fifo configuration fifo type endpoint address programmable function transmit 0 64 bytes control transfers transmit 5 64 bytes interrupt and bulk transfers transmit 6 64 bytes interrupt and bulk transfers transmit 7 2 kbytes isochronous, interrupt, and bulk transfers receive 0 64 bytes control transfers receive 1 64 bytes bulk transfers receive 2 64 bytes bulk transfers receive 3 2 kbytes isochronous and bulk transfers
n W712 usb device controller n 8 oki semiconductor application interface the application interface uses an i486-like bus to interface between the customer? module and the W712. by using an i486-like bus protocol, the W712 can be easily integrated into any customer-designed module. the integration is limited only by the available gates and i/o pins in the array. the customer application module may have its own external i/o, which do not interface with the W712. all application interface signals are unidirectional, and are either inputs or outputs of the W712. frame timer synthesizer this block synthesizes the sof signal in the event of a sof token is lost. remote wakeup this block provides support for the remote wakeup function. usb transfers the W712 supports all four transfer types defined by the usb specification. these are: control, isochro- nous, interrupt, and bulk. control transfers must be supported by every peripheral for configuration, command and status information flow between the host and peripheral. isochronous transfers provide guaranteed bus access and constant data rates for usb devices. interrupt transfers support human input devices that need to communicate small amounts of data infrequently. bulk transfers enable devices to transfer large amounts of data as bus bandwidth becomes available. usb interface the W712 connects to the universal serial bus via oki? universal usb transceivers. the usb specific i/o converts the W712? internal unidirectional signals into compliant usb signals. the universal usb trans- ceiver allows the designers?application module to interface with the physical layer of the universal serial bus. it transmits and receives serial data at both full-speed (12mb/s) and low-speed (1.5mb/s) data rates. see appendix for oki? usb transceiver data sheets.
n W712 usb device controller n 9 oki semiconductor glossary term explanation bandwidth the amount of data transmitted per unit of time, typically bits per second (bps) or bytes per second (bps). bit a unit of information used by digital computers. represents the smallest piece of addressable memory within a computer. a bit expresses the choice between two possibilities and is typically represented by a logical one (1) or zero (0). bit stuffing insertion of a ??bit into a data stream to cause an electrical transition on the data wires allowing a pll to remain locked. bulk transfer nonperiodic, large burst communication typically used for a transfer that can use any available bandwidth and also be delayed until bandwidth is available. control transfer one of four universal serial bus transfer types. control transfers support configuration/command/status type communications between client and function. crc see cyclic redundancy check. cyclic redundancy check a check performed on data to see if an error has occurred in transmitting, reading, or writing the data. the result of a crc is typically stored or transmitted with the checked data. the stored or transmitted result is compared to a crc calculated for the data to determine if an error has occurred. device endpoint a uniquely identifiable portion of a universal serial bus device that is the source or sink of information in a communication flow between the host and device. endpoint see device endpoint. interrupt transfer one of four universal serial bus transfer types. interrupt transfers characteristics are small data, non-periodic, low frequency, bounded latency, device initiated communication typically used to notify the host of device service needs. isochronous transfer one of four universal serial bus transfer types. isochronous transfers are used when working with isochronous data. isochronous transfers provide periodic, continuous communication between host and device. non-return-to-zero-invert a method of encoding serial data in which ones and zeroes are represented by opposite and alternating high and low voltages where there is no return to zero (reference) voltage between encoded bits. eliminates the need for clock pulses. nrzi see non-return-to-zero-invert. pll phase locked loop. a circuit that acts as a phase detector to keep an oscillator in phase with an incoming frequency. protocol a specific set of rules, procedures, or conventions relating to format and timing of data transmission between two devices. transaction the delivery of service to an endpoint. consists of a token packet, optional data packet, and optional handshake packet. specific packets are allowed/required based on the transaction type. transfer one or more bus transactions to move information between a software client and its function. transfer type determines the characteristics of the data flow between a software client and its function. four transfer types are defined: control, interrupt, bulk, and isochronous. universal serial bus a collection of universal serial bus devices and the software and hardware that allow them to connect the capabilities provided by functions to the host. universal serial bus interface the hardware interface between the universal serial bus cable and a universal serial bus device. this includes the protocol engine required for all universal serial bus devices to be able to receive and send packets. usb see universal serial bus.
n W712 usb device controller n 10 oki semiconductor
n W712 usb device controller n 11 oki semiconductor appendix 0.5 m m msm13r0000 sog and msm98r000 csa usb i/o library data sheets the following section contains usb i/o library data sheets
n W712 usb device controller n 12 oki semiconductor
0.5 m m sea of gates-msm13r0000 oki semiconductor msm13r-rel. 1.0 bud2sll usb i/o buffer with full / low speed cell count 4 i/o 2 pads bud2sll logic symbol truth table input output 0 1 yb gn z 1 0 1 ybn 1 0 z 1 0 0 yd yb ybn - - - - - - a an x x x x x x eb 0 0 x 1 0 0 1 -- -- 01 1 0 1 0 1 00 00x x 11 11 1 1 1 -- -- 0 0 0 0 yyn 0 1 x 1 0 x 01 0 1 00 11 s 0 0 0 0 0 0 0 0 1 - 1 0 1 1 0 - 1 0 0 - - - - x x x x 0 0 1 1 0 0 1 -- -- 01 1 0 1 0 1 00 00x x 11 11 1 1 1 -- -- 0 0 0 0 0 1 1 0 01 0 1 00 11 1 1 1 1 1 1 1 note: s=0: low speed function s=1: full speed function pin definition name type a yd in out fan-in fan-out (max.) - - an in 2.9 2.9 - 43 eb in 3.0 - gn in 7.3 - yb ybn i/o i/o - - - - y out - 40 yn out - 40 eb i o o a an ybn yb yd gn i i y yn s s in 5.8 - 0 0 1 1 00 11 -1 - 1 1 1 - 1 - 1 1 1 - 1 - 1 1 1 01 0 1 00 11 xx z 1 z 1 -- 0 1 xx 01 0 1 00 11
0.5 m m sea of gates-msm13r0000 oki semiconductor msm13r-rel. 1.0 bud2sll usb i/o buffer with full / low speed cell count 4 i/o 2 pads bud2sll a yb an ybn eb yb eb ybn lh hl lh hl lz zl zh hz lz zl zh hz - - - - - - - - - - - - 4.550 0.608 4.261 0.238 1.191 0.152 4.774 0.149 3.193 0.165 1.221 0.068 4.569 0.498 4.246 0.237 1.194 0.366 4.773 0.145 3.703 0.407 0.692 0.098 from to lh/hl tpd0' (ns) a (ns/fo) g (ns/pf) s=1: full speed delay parameters (vdd = 3.3v,tj=25 c) from to lh/hl yb lh hl tpd0' (ns) a (ns/fo) g (ns/pf) lh gn yd yd hl ybn lh hl yd yb lh hl 0.480 1.033 y 0.022 0.591 0.032 0.767 ybn lh hl yn 1.658 1.593 0.668 1.230 0.021 0.582 0.016 0.384 0.021 0.582 0.016 0.378 1.658 1.593 0.021 0.582 0.016 0.384 0.480 1.033 0.022 0.591 0.032 0.767 from to lh/hl tpd0' (ns) a (ns/fo) g (ns/pf) a yb an ybn eb yb eb ybn lh hl lh hl lz zl zh hz lz zl zh hz - - - - - - - - - - - - 113.448 0.082 112.385 0.071 1.992 0.190 2.567 0.071 1.496 0.215 70.919 0.082 121.419 0.082 112.658 0.071 2.516 0.190 2.798 0.071 2.562 0.215 67.373 0.082 s=0: low speed gn yb gn ybn lz zl zh hz lz zl zh hz - - - - - - - - 1.853 0.190 2.127 0.071 1.335 0.215 93.127 0.082 2.401 0.190 2.367 0.071 2.401 0.215 89.655 0.082 note: #1 = full speed function yb: rpd=15k w , rpu=1.5k w ybn: rpd=15k w #2 = low speed function yb: rpd=15k w ybn: rpd=15k w , rpu=1.5k w output switching parameters (vdd = 3.3v,tj =25 c) output yb tr0 (ns) g r (ns/pf) tf0 (ns) g f (ns/pf) ybn 1.822 2.041 1.491 1.821 0.095 0.090 0.105 0.087 yb ybn 79.749 77.070 136.166 78.704 0.106 0.055 0.001 0.085 #1 #2 #1 #2 power dissipation (vdd = 3.3v,tj =25 c) s=0:low speed function ac: 2940.4 m w/mhz dc: 311.2 m w yb=vih=3.3v, ybn=vil=0v 1730.9 m w(#2) yb=voh 3 2.8v, ybn=vol 0.3v 1353.8 m w(#2) yb=vol 0.3v, ybn=voh 3 2.8v 0.0 m w when power down mode(gn=1) is used s=1:full speed function ac: 48.0 m w/mhz dc: 311.2 m w yb=vih=3.3v, ybn=vil=0v 1009.4 m w(#1) yb=voh 3 2.8v, ybn=vol 0.3v 723.4 m w(#1) yb=vol 0.3v, ybn=voh 3 2.8v 0.0 m w when power down mode(gn=1) is used dc parameters (vdd: core/io = 3.3/3.3v 0.3v,tj = 0 to 85 c) parameter value conditions vdi 0.2v - voh 2.8v vol 0.3v note: vdi = differential input sensitivity vt+ 2.0v vt- 0.8v - - 15k w to gnd 1.5k w to 3.6v
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 1995 oki semiconductor oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnished by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of oki. references see the usb specification revision 1.0 for more information on usb functionality.

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